Advances in amorphous gate oxide technologies are severely limited by the inability to adequately model the full gate oxide stack structure. In addition, amorphous oxides are very challenging to understand because experimental techniques that would allow us to precisely determine their structure, and the structure of their defects, simply do not exist. Fortunately, however, electrical measurements of amorphous oxides can give quite precise information on the electronic structure of both the bulk oxide and the oxide/semiconductor interface. In order to both confirm and understand these experimental findings we need high quality models that can identify the atomic structures that correspond to the measured electronic structures. Furthermore, before these proposed devices can be realized, process models are required that would act as a guide in the fabrication of high-k amorphous oxide stacks with fewer defects. Our goal is to provide the models of high-k amorphous oxide stacks on high mobility materials so that we can develop a basic chemical understanding of which amorphous oxides and passivants can be used to form low defect gate oxides on a given semiconductor material.